Bolgatty

Experience : 15+ Years

Qualification : BTech/MTech/PhD

As SoC Design Architect, the candidate is expected to have prior experience in defining the Architecture, methodology flow and RTL implementation and SoC Integration.

The candidate also should have end to end execution experience from Design spec definition to post silicon bringup.

The candidate will meet regularly with other functional team members such as Architects, RTL and DFT Engineers, Verification Engineers, Physical Designers, CAD Engineers, Product Engineers and Program Management to ensure successful and timely project completion.

KEY RESPONSIBILITIES: 

• Participate in the development of SoC architecture solutions, and analyse implementation trade-offs
• Evaluation of third party IP to check the functional feasibility and PPA targets
• Define architecture for next-gen ASICs (RISC V) including processor system, IO Peripherals, platform management, interconnect, and memory subsystem
• Define architecture specifications in a clear and concise language
• Implementation of design in RTL, SoC Integration etc.
• Collaborate with cross functional teams – DFT, DV and Physical Implementation teams
• Collaborate with program management to specify requirements
• Work with other architects, design/verification, and software for the IP development & acquisition

PREFERRED EXPERIENCE:

• Strong foundation in SoC architecture and processor systems with proven years of experience
• Proven experience in RISC-V based multicore SoC
• Excellent understanding of Embedded Software architecture (Bare Metal, Linux)
• Excellent knowledge of CPU, AXI Interconnect, and I/O peripherals
• Good analytical problem solving, and attention to details
• Working knowledge of C, SystemVerilog, and Python
• Excellent written and verbal communication skills
• Knowledge of SOC development flow and accelerator IP
• Experience in micro-architecture and digital design/verification
• Knowledge of power management, boot, security and memory architectures
• Exposure to performance modelling and analysis will be a plus