JD1328 : Design Verification Engineer with Specman and UVM
Experience : 3+ Years
Detailed Jd Below :
- Develop and implement verification plans and strategies for complex semiconductor designs using Specman and UVM
- Design and maintain verification environments, including testbenches and test cases
- Write and execute test sequences, monitor results, and debug failures
- Collaborate with design and architecture teams to identify potential issues and ensure comprehensive coverage
- Perform regression testing and analyze results to continuously improve verification quality
- Provide documentation and support for verification processes and methodologies
- 5+ years of experience in design verification
- Proficient in Specman e and UVM
- Strong understanding of verification methodologies and best practices
- Experience with creating and maintaining complex verification environments
- Solid understanding of digital design and HDL (Verilog/VHDL)
- Proficiency in scripting languages (Python, Perl, etc.) is a plus
- Preferred: Experience in verifying complex IPs or SoCs
- Preferred: Knowledge of formal verification techniques
- Preferred: Familiarity with EDA tools and simulators (Cadence, Synopsys, Mentor Graphics)
Job Location: Bangalore
