Bolgatty

Experience : 5+ Years

Detailed JD Below :

• Perform physical design tasks including floor planning, placement, clock tree synthesis, routing, and optimization.
• Collaborate with design and verification teams to achieve optimal PPA (Power, Performance, Area) goals.
• Utilize industry-standard EDA tools for physical design and sign-off (e.g., Cadence, Synopsys, Mentor Graphics).
• Conduct timing closure and static timing analysis (STA) to ensure design meets performance targets.
• Perform power analysis and optimization to achieve low-power design goals.
• Implement DFT (Design for Test) methodologies to ensure manufacturability and testability.
• Resolve physical design issues such as congestion, timing violations, and design rule violations (DRC).
• Conduct physical verification tasks including LVS (Layout Versus Schematic) and DRC checks.
• Interface with fabrication partners to address manufacturing-related issues.
• Develop and maintain physical design methodologies and best practices.
• Create and maintain physical design documentation and reports.
• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
• Strong understanding of VLSI design principles and semiconductor physics.
• Proficiency in physical design tools (e.g., ICC2, Innovus, PrimeTime).
• Experience with scripting languages (Python, TCL, Perl) for automation and tool customization.
• Knowledge of process technology nodes and their impact on physical design.
• Experience with advanced node technologies (e.g., 7nm, 5nm) is a plus.
• Familiarity with low-power design techniques and methodologies.
• Knowledge of packaging and PCB design considerations.