Bolgatty

Experience : 7+ Years

Location : Bangalore

Detailed JD :

• Understanding of DFT (Design for Test) architectures like JTAG (Joint Test Action Group)
• Proficiency in Scan Compression Techniques
• Experience with Synopsys tools for DFT
• Strong knowledge of design for test principles and methodologies
• Ability to develop and implement DFT strategies for complex SoCs
• Experience in generating and validating test patterns for manufacturing test
• Proficiency in writing and debugging test programs
• Familiarity with boundary scan testing and IEEE 1149.x standards
• Skilled in ATPG (Automatic Test Pattern Generation) and fault simulation
• Experience with design rule checks and test coverage analysis
• Knowledge of BIST (Built-In Self-Test) techniques for memory and logic
• Ability to work closely with design and verification teams to integrate DFT features
• Strong problem-solving skills for identifying and resolving DFT-related issues
• Proficiency in scripting languages (e.g., Tcl, Perl, Python) for automation tasks
• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field
• Willingness to stay updated with the latest DFT tools and techniques
• Ability to manage and lead DFT projects and ensure timely delivery of testable designs
• Experience with hierarchical DFT implementation
• Knowledge of low power DFT techniques and practices
• Ability to perform DFT audits and reviews to ensure best practices are followed
• Experience in post-silicon debug and validation

Must to Have :

• Understanding of DFT architectures like JTAG, Understanding of Scan Compression Techniques, Synopsys tool experience.