Bolgatty

Experience : 4+ Years

Location : Bangalore

Detailed JD Below :

• Develop comprehensive verification plans based on design specifications and requirements.
• Design and implement testbenches using industry-standard verification languages such as SystemVerilog and UVM.
• Create and maintain test cases to validate the functionality and performance of SOC designs.
• Perform simulations and debug failures to root cause issues in the SOC design.
• Work closely with design and architecture teams to understand the functionality and features of the SOC.
• Utilize and enhance verification environments, including testbenches, stimulus generation, and checkers.
• Ensure thorough coverage and implement coverage-driven verification methodologies.
• Develop and use scripts to automate verification processes and improve efficiency.
• Participate in design and verification reviews, providing feedback and insights to improve design quality.
• Document verification processes, methodologies, and results.

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• Proven experience in SOC verification with a strong understanding of verification methodologies (UVM, OVM, etc.).
• Proficiency in SystemVerilog and other hardware description and verification languages.
• Experience with simulation tools (e.g., Cadence Incisive, Mentor Graphics Questa, Synopsys VCS).
• Familiarity with scripting languages such as Python, Perl, or Tcl.
• Strong analytical and problem-solving skills.
• Excellent communication and teamwork abilities.
• Detail-oriented with a focus on quality and thoroughness.

Preferred Qualifications

• Experience with SOC integration and system-level verification.
• Knowledge of low-power design techniques and verification.
• Familiarity with software/hardware co-verification.
• Experience with formal verification methods.
• Understanding of digital design fundamentals and computer architecture.